1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a test function.
2. Description of the Background Art
A semiconductor integrated circuit containing a redundancy circuit (a spare memory) has conventionally been known.
Japanese Patent Laying-Open No. 1-224998, for example, discloses a semiconductor integrated circuit including a memory array having a decoder, a first control circuit generating an address, a read/write control signal, write data, read expected data in response to a control clock when a test mode is set by an external control pin, a first comparator comparing a result of reading the memory array with the read expected value data, an address register storing a corresponding address when an output of the first comparator indicates disagreement, a second comparator comparing an address in the address register with an external address in a normal operation, and a second control circuit switching between the memory array and the spare memory to be accessed in accordance with an output result of the second comparator.
The aforementioned Japanese Patent Laying-Open No. 1-224998, however, has the following problems.
First, address registers are required by the number of redundancy circuits. This results in a larger scale of the semiconductor integrated circuit.
Furthermore, when the number of errors, that is, the number of times the read result differs from the read expected values is larger than the number of redundancy circuits, the addresses causing the excessive errors cannot be stored in the address register and therefore all of the locations of the memory cells causing errors cannot be specified.